Good. Assuming also, that the CPU chip is correctly marked.cream51 wrote: Wed Dec 24, 2025 8:48 am i tryed some changes on my cpu board, the processor is an EF68B09EP, so no oscillator on he chip
i removed the JP2, just connected on 1 side.
I did have some issues with falsely re-marked 6809 chips. i.e. 6809P that were really 6809EP, and 6809EP that were really 6809P (although this is rarer as the 6809EP are more common).
JP1 Jumper should be on! It is the ROM Write Enable, which (by default), you want the jumper on 'RO' (Read Only), which pulls-up the Write / Program pin.
This switch setting is correct for $C0xx IORQ bank. Which matches well with the 48K + 16K Memory Map (indicated on you PLD label).cream51 wrote: Wed Dec 24, 2025 8:48 am sw2 is A15 and A14 is off-------- A13,1A12,A11,A10,A9,A8 is ON
However, you still have the issue of possibly using an ASSIST09 ROM assembled for the 56K + 8K Memory Map, also expecting the IORQ Bank to be at $E0xx.
The original ASSIST09 (with this 56K/8K configuration), expects RAM to extend to $DFFF (where the Stack and Workspace is located).
To resolve this you will either need to re-program the ROM with a 48K/16K/C0 varient of ASSIST09 (.bin image available from MECB Github),
OR, re-program the PLD chip for the 56K/8K Memory map (.jed file also available from MECB Github).
To program either the ROM or the PLD will require a EPROM Programmer like the TL866 series (which hopefully you have handy?).