This is helpful, as I was just about to query the requirement for the CLK2 / CLK4 pins.epaell wrote: Tue Mar 24, 2026 11:08 pm BTW, I realise that I didn't really label the "mysterious" J2 header on the Z80 board very well. I use the GAL to divide the CPU clock by 2 and 4 and use the J2 jumper to select between the full CPU clock, or the /2 or /4 alternative. With anything too high (e.g. I currently have a 10 MHz CPU) it tends to prevent the 6840 timer from operating so I normally add a jumper in the middle of the 2x3 header to select the /2 clock (top two pins select the highest clock rate, middle two the /2 clock and the bottom two the /4 clock).
I had noticed that the bus MREQ isn’t implemented (in the PLD logic). Presumably, because all of the memory is on-board, so the bus is just being used for I/O?
It had occurred to me that you are not using the generated MA20 & MA21, so I just thought it would have been nice if these (MA16 - MA21), could be wired into the bus (for a 4MB memory address space), which would also require wiring MA20 & MA21 into the PLD (hence my question about the need for the CLK2 & CLK4 pins)
This would allow the 1MB for on-board memory, and the remaining 3MB to be available via the bus (via the bus MREQ), for memory mapped expansion cards (or simply bus based memory expansion).
In terms of the problem of 6840 PTM IORQ clock speed capability, perhaps the solution to this would be to instead use the upcoming WDC I/O Card (specifically the VIA’s timer), as these modern WDC peripheral chips are cable of faster speed? Assuming a 65C22 timer could be supported in place of a PTM?
Just some thoughts…
Also (seperate note)…
I’ve just been made aware of MicroChip AN0484 “Selecting Decoupling Capacitors for PLDs”, which highly recommends the use of 220nf bypass capacitors with their PLDs (instead of my usual 100nf go to).
https://www.microchip.com/en-us/applica ... tes/an0484
Having read the recommendation, I’m now changing my PLD specific bypass capacitor use to 220nf.
Note that I’ve never experienced (or measured), any issues with power line noise on my MECB systems, but when you read a manufacturer application note than has a specific recommendation, it’s usually worthy of note.
Therefore, I’ve already updated the PCBs of a couple of my Cards (for future PCB orders), and I will be using 220nf for PLD bypass, in future.